Dynamic random access memories (DRAM) are the most commonly manufactured product of all semiconductor integrated circuits (ICs). DRAMs are data storage devices that store data as a charge on a storage capacitor. A DRAM typically includes an array of memory cells. Each memory cell includes a storage capacitor and a transistor for transferring charge to and from the storage capacitor. Each memory cell is addressed by a word line (WL) and accessed by a bit line (BL) pair. The WL controls the transistor such that the transistor couples the storage capacitor to and decouples the storage capacitor from the BL pair for writing data to and reading data from the memory cell. Multiple word lines correspond to multiple rows of memory cells, while multiple bit line pairs correspond to multiple columns of memory cells.
Word line/bit line (WL/BL) shorts are the most common failure mode in DRAMs, especially when self-aligned BL contacts are used. These shorts create a leakage path from the output of the WL driver via the equalize (EQL) transistor to the equalize voltage, causing a constant current flow and charging the generator system. More specifically, during standby mode, paired BLs are kept at a preset bit line precharged potential. Generally, the precharge potential is set to half the high level potential of the BL. At this time, the potential of the WL is set at a low level. Therefore, when a WL/BL short occurs, a leakage current will continuously flow from the BL which is set at the preset precharge potential to the WL which is set at a low level potential, such as ground. As a result, the potential of the BL which is short-circuited to the WL is lowered. The amount of lowering in the BL potential depends on a resistance between the short-circuited BL and WL and the conductance of a precharge current limiting element, if any, connected to the BL. The output voltage of the WL driver is either high or low, depending on operational conditions. The equalize voltage is high, ground (GND), or mid-level, depending on the sensing scheme. Used in this context, “low” indicates zero (GND), slightly above zero, or below zero (e.g., VWLL=−0.5 volts). In any case, there is at least one operational condition where a leakage current causes additional load to the on-chip generator system. This additional load leads to reduced voltage levels and can cause a portion or all of the DRAM to malfunction.
FIG. 1 diagrammatically illustrates a word line/bit line (WL/BL) short 160 in array word line transistor arrangement 100 with grounded equalize 132, 137 and sense amplifier 150 as known in the art. Transistor 125 and capacitor 127 form array cell 120. The source of transistor 125 is connected to capacitor 127. Capacitor 127 is then connected to plate 129, which is preferably held at half the high level potential of BLt 130. The gate of transistor 125 is connected to word line (WL) 140 of the row in which cell 120 is located. The drain of transistor 125 is connected to a bit line (BL), BLt 130, of the column in which cell 120 is located. BLt 130 includes BLt EQL transistor 132, connected to ground 170. A complementary BL, BLc 135, is also provided for the column in which cell 120 is located. BLc 135 includes BLc EQL transistor 137, connected to ground 170. Conventionally, EQL 132 and 135 are regular N-Channel Junction Field-Effect Transistors (“NFETs”). BLt 130 and BLc 135 comprise a BL pair. EQL 132, 137 charges BLt 130 and BLc 135 to the EQL voltage. A value read out of cell 120 onto BLt 130 is amplified by sense amplifier 150. SAEQ 152 is used to shorten BLt 130 and BLc 135. WL/BL short 160 has a current path from the output 115 of WL driver 110, which is tied to VWLL 108 via NFET transistor 106, through WL/BL short 160 across BLt EQL transistor 132 to ground 170.
FIG. 2 diagrammatically illustrates a word line/bit line (WL/BL) short 160 in an array word line transistor arrangement 200 with grounded equalize 132, 137 and shared sense amplifier 250 as known in the art. In the conventional embodiment of FIG. 2, a current path parallel to the path described with reference to FIG. 1 is formed across BLt isolator (ISO) transistor 282, SAEQ transistor 252, BLc ISO transistor 287 and BLc EQL transistor 137 to ground 170. Conventionally, ISO 282 and 287 are thick oxide NFETs. VWLL 108 is a small negative voltage (e.g., −0.5 volts), but can still cause a leakage current of up to 110 μA per WL/BL short 160 while operating in precharge mode. A special problem occurs when a shared sense amplifier, such as shared sense amplifier 250, is used; not only does WL/BL short 160 adversely affect BLt 130, but the operation margin of BLc 135 is reduced. However, since the amount of the reduction is small in comparison with BLt 130, it becomes extremely difficult to detect BLc 135 through the conventional screening process. As a result, a semiconductor memory device containing a WL/BL short, such as WL/BL short 160, can be subjected to post processing without a replacement of the shorted BL, such as BLt 130. The defect may not be detected until after the semiconductor memory device has been assembled into a package. It may even ship as product before being detected.
FIGS. 3 and 4 diagrammatically illustrate different views of FIG. 2. FIG. 3 diagrammatically illustrates shared sense amplifier arrangement 300 with equalize transistors, EQL Top 332a-n, 337a-n and EQL Bottom 334a-n, 339a-n, and isolator transistors, ISO Top 382a-n, 387a-n and ISO Bottom 384a-n, 389a-n, as known in the art. BL pairs 330a-n, 335a-n and 333a-n, 336a-n provide access to all cells in the arrays, while WLs 340a-m address array rows a-m, respectively. ISO Top 382a-n, 387a-n are in BL pairs 330a-n, 335a-n, respectively, between array 31 and shared sense amplifier 350. ISO Bottom 384a-n, 389a-n are in BL pairs 333a-n, 336a-n, respectively, between shared sense amplifier 350 and array 32. EQL Top 332a-n, 337a-n, in BL pairs 330a-n, 335a-n, respectively, are connected to ground. EQL Bottom 334a-n, 339a-n, in BL pairs 333a-n, 336a-n, respectively, are connected to ground.
FIG. 4 diagrammatically illustrates a leakage path to ground 470 via equalize (EQL) 432 and isolator (ISO) 482 transistor diffusion as known in the art. The cross-sectional view of FIGS. 2 and 3 shown in FIG. 4 includes WL/BL short 160 at the intersection of WL 440 and BL 430 between ISO 482 and EQL 432, with a leakage path to ground 470. In addition to the transistor current, a forward biased diode current from both EQL 432 and ISO 482 transistor diffusion contributes to the overall leakage current. Therefore, even if EQL 432 and ISO 482 transistors are turned off (e.g., gate at VWLL), in some operational states the forward biased diode current can still cause a leakage path to ground 470. Isolated p-well 410 is created by placing a p-well inside n-well (NW) 415, resulting in a third type of well structure: triple well (TW) 420. TW 420 uses the reverse bias between NW 415 and p-substrate 405 to electrically isolate individual DRAM and logic circuit sections to minimize mutual interference. TW 420 enables independent optimization of all device types on a chip (e.g., logic, SRAM or DRAM), as well as improved isolation from substrate noise. In the conventional embodiment of FIG. 4, ISO 482 and EQL 432 are connected via BL 430 and are located at opposite ends of and external to TW 420. P-well contact 450 is within isolated p-well 410, while n-well contacts 460a and 460b are at opposite ends of NW 415, near ISO 482 and EQL 432, respectively.
Known concepts for reducing leakage caused by WL/BL shorts, such as WL/BL short 160 shown in FIGS. 1, 2 and 4, include placing current limiter transistors between the array transistor, such as transistor 125, and the EQL transistors, such as EQL 132, 137. The current limiter transistor is designed with three (3) or four (4) times the nominal gate length and is tied to an internal voltage (e.g., VINT) which is the nominal operational voltage. Prior art designs intentionally utilize the current limiter transistor to limit the current, but not to completely avoid the leakage. FIG. 9 diagrammatically illustrates a word line/bit line short 160 with current limiter transistors 910 and 920 in an equalize path as known in the art. The primary difference between the conventional embodiment of FIG. 1 and the conventional embodiment of FIG. 9 is the addition of current limiter transistors (VCULI) 910 and 920 connected to EQL 132, 137, respectively, opposite ground 170, in BLt 130 and BLc 135, respectively.
It is therefore desirable to provide a solution that avoids leakage caused by word line/bit line shorts. The present invention attempts to avoid such leakage by providing one or more of the transistors (e.g., isolator, current limiter and equalize) inside an isolated p-well.